SEU and SET-tolerant ARM Cortex-R4 CPU for Space and Avionics Applications

Soft errors induced by radiation, causing anomalies in satellite equipment and spacecrafts, have become one of the most challenging issues that impact the reliability of modern processors even in ground-level applications. In this work, we investigate the feasibility of using ARM Cortex-R4 CPU for space and avionics applications. We create a single-event upset and transient tolerant variant Cortex-R4 CPU without modifying the original CPU microarchitecture. We do this by applying the Triple Modular Redundancy (TMR) techniques to all sequential elements at gate-level. We present the implementation methodology, power, area and performance overheads of Cortex-R4-TMR normalized to a baseline Cortex-R4, without TMR.